ICE - Institute for Communication Technologies and Embedded Systems: Entry ICE - Institute for Communication Technologies and Embedded Systems: Entry

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How to guarantee deterministic behavior in parallel simulations How to achieve thread-safety in parallel simulations In cooperation with Synopsys, Inc. Parallel SystemC simulation parSC splits a tightly-coupled MPSoC simulation over a multi-core host, to make use of the computation power such machines provide.

The programming model is constructed in a way that these models already fulfilled the requirements for safe and deterministic integration.

The only work required was to augment the simulation structure declared during SystemC elaboration with a couple of utility classes.

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A programming model has been found that fulfills these requirements. The mission of the parSC technology is to provide a fast, deterministic and accurate simulation framework to increase developer productivity.

In the beginning, experimentation was conducted using models that have been coded with the constraints of a parallel execution environment in mind. Therefore the known instruction set simulation techniques which work well for single processors need to be revised such that they can scale well for massively parallel platforms.

Research is ongoing regarding the adaptation of the technology to use-cases without stringent accuracy and determinism requirements.

In the long run, though, it will be required to have a way to reuse an existing legacy code base in paralllel simulation environments.

In such a way the accuracy at the level of the original simulation is completely maintained, and the speed-up is gained by exploiting the parallel computing power of the host. Currently, research is conducted at ICE regarding the following closely related issues: The new programming model and the set of required parallel SystemC kernel extensions, together with a set of utility classes, form the legaSCi methodology.

The implementation is optimized utilizing techniques from the high-performance computing domain, to reduce host inter-core communication latency to make fully-interlocked simulations with fast instruction set simulators feasible.

Parallelization is therefore taking place over individual SystemC delta cycles.

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Due to this programming model, models of the network processor and peripherals could be integrated into the parallel simulator. With the parSC kernel as a base, the focus of recent research has shifted to the programming model of SystemC models to be used inside a parallel simulator.

The execution is fully synchronous, enforcing the same global time to all SystemC processes.

The execution model of parSC is such that the SystemC event loop is preserved, and is led by a master thread which decides if there is work to be offloaded to worker threads, in which case they just execute the inner iteration loop of the main evaluation loop of SystemC.

In order to utilize such complex architectures maximally, powerful tools would need to be provided, with a good simulator at their core. Systems that can be partitioned into distinct parts without highly frequent communication in between, as is the case for the tiled EURETILE system, are good candidates for successful acceleration using legaSCi.

At the same time, such programming models need to be simple enough so that they do not impact the model creators' producivity, and as well allow the adaptation and employment of existing legacy models in parallel simulations.